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d a t a sh eet product speci?cation supersedes data of 2002 nov 15 2003 feb 18 integrated circuits tda8007b double multiprotocol ic card interface
2003 feb 18 2 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 interface control 8.1.1 multiplexed configuration 8.1.2 non-multiplexed configuration 8.2 control registers 8.2.1 general registers 8.2.2 iso uart registers 8.2.3 card registers 8.2.4 register summary 8.3 supplies and voltage supervisor 8.4 step-up converter 8.5 iso 7816 security 8.6 activation sequence 8.7 deactivation sequence 9 limiting values 10 handling 11 thermal characteristics 12 characteristics 13 timing 14 application information 15 package outline 16 soldering 16.1 introduction to soldering surface mount packages 16.2 reflow soldering 16.3 wave soldering 16.4 manual soldering 16.5 suitability of surface mount ic packages for wave and reflow soldering methods 17 data sheet status 18 definitions 19 disclaimers
2003 feb 18 3 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 1 features control and communication through an 8-bit parallel interface, compatible with multiplexed or non-multiplexed memory access specific iso uart with parallel access input/output for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for t = 0 and extra guard time register fifo for 1 to 8 characters in reception mode parity error counter in reception mode and in transmission mode with automatic re-transmission dual v cc generation: 5 v 5%, 65 ma (max.); 3v 8%, 50 ma (max.) or 1.8 v 10%, 30 ma (max.); with controlled rise and fall times dual cards clock generation (up to 10 mhz), with three times synchronous frequency doubling (f xtal , 1 / 2 f xtal , 1 / 4 f xtal and 1 / 8 f xtal ) cards clock stop (at high or low level) or 1.25 mhz (from internal oscillator) for cards power-down mode automatic activation and deactivation sequence through an independent sequencer supports the asynchronous protocols t = 0 and t = 1 in accordance with: C iso 7816 and emv 3.1.1 (tda8007bhl/c2 and tda8007bhl/c3) C iso 7816 and emv 2000 (tda8007bhl/c3) versatile 24-bit time-out counter for answer to reset (atr) and waiting times processing specific elementary time unit (etu) counter for block guard time (bgt): 22 in t = 1 and 16 in t = 0 minimum delay between two characters in reception mode: C in protocol t = 0: 12 etu (tda8007bhl/c2) 11.8 etu (tda8007bhl/c3) C in protocol t = 1: 11 etu (tda8007bhl/c2) 10.8 etu (tda8007bhl/c3) supports synchronous cards current limitations in the event of short-circuit (pins i/o1, i/o2, v cc1 , v cc2 , rst1 and rst2) special circuitry for killing spikes during power-on/power-off supply supervisor for power-on/power-off reset step-up converter (supply voltage from 2.7 to 6 v), doubler, tripler or follower according to v cc and v dd additional input/output pin allowing use of the iso uart for another analog interface (pin i/oaux) additional interrupt pin allowing detection of level toggling on an external signal (pin intaux) fast and efficient swapping between the three cards due to separate buffering of parameters for each card chip select input allowing use of several devices in parallel and memory space paging enhanced esd protections on card side: 6 kv (min.) software library for easy integration within the application power-down mode for reducing current consumption when no activity. 2 applications multiple smart card readers for multiprocessor applications (emv banking, digital pay tv and access control, etc.). 3 general description the tda8007bhl/c is a cost-effective card interface for dual smart card readers. controlled through a parallel bus, it meets all requirements of: iso 7816, gsm 11-11 and emv 3.1.1 (tda8007bhl/c2 and tda8007bhl/c3) iso 7816, gsm 11-11 and emv 2000 (tda8007bhl/c3). it may be interfaced to the ports p0, p1 and p2 of a 80c51 family microcontroller, and be addressed as a memory through movx instructions. it may also be addressed on a non-multiplexed 8-bit data bus, by means of address registers ad0, ad1, ad2 and ad3. the integrated iso uart and the time-out counters allow easy use even at high baud rates with no real time constraints. due to its chip select, external input/output and interrupt features, it greatly simplifies the realization of a reader of any number of cards. it gives the cards and the reader a very high level of security, due to its special hardware against esd, short-circuiting, power failure, etc. the integrated step-up converter allows operation within a supply voltage range of 2.7 to 6 v; it may be supplied with a voltage higher than the ics supply. a software library has been developed that covers all actions required for t = 0 and t = 1 and synchronous protocols (see application note an01054 ).
2003 feb 18 4 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 4 quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 2.7 - 6v v dda supply voltage for step-up converter v dd - 6v i dd(pd) supply current in power-down mode v dd = 3.3 v; cards inactive; xtal oscillator stopped -- 350 m a v dd = 3.3 v; cards active at v cc = 5 v; clk stopped; xtal oscillator stopped -- 3ma i dd(sm) supply current in sleep mode cards powered at 5 v; clock stopped -- 5.5 ma i dd(oper) supply current in operating mode v dd = 3.3 v; f xtal = 20 mhz; v cc1 =v cc2 =5v; i cc1 +i cc2 =80ma -- 315 ma v cc card supply output voltage 5 v card including static loads 4.75 5.0 5.25 v with 40 nc dynamic loads on 200 nf capacitor 4.6 - 5.4 v 3 v card including static loads 2.78 - 3.22 v with 24 nc dynamic loads on 200 nf capacitor 2.75 - 3.25 v 1.8 v card including static loads 1.65 - 1.95 v with 12 nc dynamic loads on 200 nf capacitor 1.62 - 1.98 v i cc card supply output current 5 v card; operating -- 65 ma 3 v card; operating -- 50 ma 1.8 v card; operating -- 30 ma overload detection - 100 - ma i cc1 +i cc2 sum of both card supply output currents operating; 5 and 3 v cards -- 80 ma sr slew rate on v cc (rise and fall) c l(max) = 300 nf 0.05 0.16 0.22 v/ m s t deact deactivation cycle duration -- 150 m s t act activation cycle duration -- 225 m s f xtal crystal frequency 4 - 20 mhz f ext external frequency applied to pin xtal1 0 - 20 mhz t amb ambient temperature - 40 - +85 c
2003 feb 18 5 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 5 ordering information 6 block diagram type number package name description version tda8007bhl/c2 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 tda8007bhl/c3 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 handbook, full pagewidth analog drivers and sequencers iso7816 uart interface control clock circuit step-up converter v dd gnd sap sam v dda agnd v up delay rstout int ale ad0 ad1 ad2 ad3 rd wr d0 d1 d2 d3 d4 d5 d6 d7 cs i/oaux intaux xtal1 xtal2 c41 1 48 40 39 45 44 43 42 36 37 28 29 30 31 32 33 34 35 38 2 41 47 46 15 13 11 17 18 16 12 14 7 5 3 9 10 8 4 6 20 25 24 22 26 21 23 19 27 clk1 c81 rst1 v cc1 pres1 i/o1 cgnd1 c42 clk2 c82 rst2 v cc2 pres2 i/o2 cgnd2 100 nf supply and supervisor int osc tda8007b xtal osc fce534 220 nf 220 nf 22 nf sbp sbm 220 nf time-out counter fig.1 block diagram.
2003 feb 18 6 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 7 pinning symbol pin description rstout 1 pmos open-drain output for resetting external devices i/oaux 2 input or output for an i/o line from an auxiliary smart card interface i/o1 3 input or output for the data line to/from card 1 (iso c7 contact) c81 4 auxiliary i/o for iso c8 contact (synchronous cards, for instance) for card 1 pres1 5 card 1 presence contact input (active high) c41 6 auxiliary i/o for iso c4 contact (synchronous cards, for instance) for card 1 cgnd1 7 ground for card 1; must be connected to gnd clk1 8 clock output to card 1 (iso c3 contact) v cc1 9 card 1 supply output voltage (iso c1 contact) rst1 10 card 1 reset output (iso c2 contact) i/o2 11 input or output for the data line to/from card 2 (iso c7 contact) c82 12 auxiliary i/o for iso c8 contact (synchronous cards, for instance) for card 2 pres2 13 card 2 presence contact input (active high) c42 14 auxiliary i/o for iso c4 contact (synchronous cards, for instance) for card 2 cgnd2 15 ground for card 2; must be connected to gnd clk2 16 clock output to card 2 (iso c3 contact) v cc2 17 card 2 supply output voltage (iso c1 contact) rst2 18 card 2 reset output (iso c2 contact) gnd 19 ground v up 20 connection for the step-up converter capacitor; connect a low esr capacitor of 220 nf to agnd sap 21 contact 1 for the step-up converter; connect a low esr capacitor of 220 nf between pins sap and sam sbp 22 contact 3 for the step-up converter; connect a low esr capacitor of 220 nf between pins sbp and sbm v dda 23 positive analog supply voltage for the step-up converter; may be higher than v dd ; decouple with a good quality capacitor to gnd sbm 24 contact 4 for the step-up converter; connect a low esr capacitor of 220 nf between pins sbp and sbm agnd 25 analog ground for the step-up converter sam 26 contact 2 for the step-up converter; connect a low esr capacitor of 220 nf between pins sap and sam v dd 27 positive supply voltage; decouple with a good quality capacitor to gnd d0 28 input/output of data 0 or address 0 d1 29 input/output of data 1 or address 1 d2 30 input/output of data 2 or address 2 d3 31 input/output of data 3 or address 3 d4 32 input/output of data 4 or address 4 d5 33 input/output of data 5 or address 5 d6 34 input/output of data 6 or address 6 d7 35 input/output of data 7 or address 7
2003 feb 18 7 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b rd 36 read selection input; read or write in non-multiplexed con?guration (active low) wr 37 write selection input; enable in case of non-multiplexed con?guration (active low) cs 38 chip select input (active low) ale 39 address latch enable input in case of multiplexed con?guration; connect to v dd in non-multiplexed con?guration int 40 nmos interrupt output (active low) intaux 41 auxiliary interrupt input ad3 42 register selection address 3 input ad2 43 register selection address 2 input ad1 44 register selection address 1 input ad0 45 register selection address 0 input xtal2 46 connection for an external crystal xtal1 47 connection for an external crystal or input for an external clock signal delay 48 connection for an external delay capacitor symbol pin description handbook, full pagewidth tda8007bhl fce678 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 delay xtal1 xtal2 ad0 ad1 ad2 ad3 intaux int ale cs wr pres2 c42 cgnd2 clk2 v cc2 rst2 gnd v up sap sbp v dda sbm rstout i/oaux i/o1 c81 pres1 c41 cgnd1 clk1 v cc1 rst1 i/o2 c82 rd d7 d6 d5 d4 d3 d2 d1 d0 v dd sam agnd fig.2 pin configuration.
2003 feb 18 8 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8 functional description throughout this specification, it is assumed that the reader is aware of iso 7816 norm terminology. 8.1 interface control the tda8007bhl/c can be controlled via an 8-bit parallel bus (bits d0 to d7). 8.1.1 m ultiplexed configuration if a microcontroller with a multiplexed address and data bus (such as the 80c51) is used, then pins d0 to d7 may be directly connected to ports p0 to p7. automatic switching to the multiplexed bus configuration (see fig.3) occurs: in tda8007bhl/c2; if a rising edge is detected on signal ale and cs is low in tda8007bhl/c3; if a rising edge is detected on signal ale. in this event, pins ad0 to ad3 play no role and may be tied to v dd or ground. when signal cs = low (see fig.4), the demultiplexing of address and data is performed internally using signal ale, a low pulse on pin rd allows the selected register to be read, a low pulse on pin wr allows the selected register to be written to. using a 80c51 microcontroller, the tda8007bhl/c is simply controlled with movx instructions. 8.1.2 n on - multiplexed configuration if pin ale is tied to v dd or ground, the tda8007bhl/c will be in the non-multiplexed configuration. in this case, the address bits are determined by means of pins ad0 to ad3; the read or write control signal is on pin rd and a data write or read active low enable signal is on pin wr. in non-multiplexed bus configuration, signals cs and wr play the same role. in read operations (see fig.5) with signal rd = high, the data corresponding to the chosen address is available on the bus when both signals cs and wr are low. in write operations (see figs.6 and 7) with signal rd = low, the data present on the bus is written when signals cs and wr are low. in both configurations, the tda8007bhl/c is selected only when signal cs = low. signal int is an active low interrupt signal. handbook, full pagewidth latch mux mux addresses fce679 rd wr rec cs ad0 to ad3 ale wr rd d0 to d7 registers fig.3 multiplexed bus recognition.
2003 feb 18 9 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth ale cs d0 to d7 rd wr fce680 t w(ale) t avll t avll address data read address data write t (rwh-ah) t (rwh-ah) t w(rd) t (dv-wl) t (al-rwl) t (al-rwl) t (rl-dv) t w(wr) fig.4 control with multiplexed bus (read and write). handbook, full pagewidth ad0 to ad3 d0 to d7 data out fce840 rd cs wr t 1 t 3 t 2 fig.5 control with non-multiplexed bus (read).
2003 feb 18 10 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth ad0 to ad3 d0 to d7 data in fce841 rd cs wr t 6 t 5 t 4 t 7 fig.6 control with non-multiplexed bus (write release with signal cs). handbook, full pagewidth ad0 to ad3 d0 to d7 data in fce842 rd cs wr t 6 t 5 t 4 t 7 fig.7 control with non-multiplexed bus (write release with signal en).
2003 feb 18 11 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2 control registers the tda8007bhl/c has two complete analog interfaces which can drive cards 1 and 2. the data to and from these two cards shares the same iso uart. the data to and from a third card (card 3), externally interfaced (with a tda8020 or tda8004 for example), may also share the same iso uart. cards 1, 2 and 3 have dedicated registers for setting the parameters of the iso uart (see fig.8): programmable divider register (pdr) guard time register (gtr) uart configuration register 1 (ucr1) uart configuration register 2 (ucr2) clock configuration register (ccr). cards 1 and 2 also have dedicated registers for controlling their power and clock configuration. the power control register (pcr) for card 3 is controlled externally. register pcr is also used for writing or reading on the auxiliary card contacts c4 and c8. card 1, 2 or 3 can be selected via the card select register (csr). when one card is selected, the corresponding parameters are used by the iso uart. register csr also contains one bit for resetting the iso uart (bit riu = 0). this bit is reset after power-on and must be set to logic 1 before starting with any one of the cards. it may be reset by software when necessary. when the specific parameters of the cards have been programmed, the uart may be used with the following registers: uart receive register (urr) uart transmit register (utr) uart status register (usr) mixed status register (msr). in reception mode, a fifo of 1 to 8 characters may be used and is configured with the fifo control register (fcr). this register is also used for the automatic re-transmission of not acknowledged (nak) characters in transmission mode. the hardware status register (hsr) gives the status of the supply voltage, of the hardware protections and of the card movements. registers hsr and usr give interrupts on pin int when some of their bits have been changed. register msr does not give interrupts and may be used in the polling mode for some operations; for this use, some of the interrupt sources within the registers usr and hsr may be masked. a 24-bit time-out counter may be started to give an interrupt after a number of etu programmed into the time-out registers tor1, tor2 and tor3. this will help the microcontroller in processing different real-time tasks (atr, wwt, bwt, etc.). this counter is configured with a time-out counter configuration (toc) register. it may be used as a 24-bit counter or as a 16-bit plus 8-bit counter. each counter can be set to start counting once data has been written, or on detection of a start bit on the i/o, or as auto-reload.
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2003 feb 18 12 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth program divider register 2 card 2 guard time register 2 uart configuration register 21 uart configuration register 22 time-out register 1 general card select register hard status register time-out register 2 time-out register 3 uart transmit register iso uart uart status register mixed status register uart receive register fifo control register time-out configuration clock configuration register 2 power control register 2 program divider register 3 card 3 guard time register 3 uart configuration register 31 uart configuration register 32 clock configuration register 3 fce682 program divider register 1 card 1 guard time register 1 uart configuration register 11 uart configuration register 12 clock configuration register 1 power control register 1 fig.8 summary of registers.
2003 feb 18 13 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.1 g eneral registers 8.2.1.1 card select register the card select register (csr) is used for selecting the card on which the uart will act, and also to reset the iso uart. table 1 register csr (address 00h; write and read); note 1 note 1. register value at reset: all significant bits are cleared after reset, except bits cs7 to cs4 which are set to their default value. table 2 description of csr bits; note 1 note 1. bits sc1, sc2 and sc3 must be set one at a time. after reset, no card is selected by default. 8.2.1.2 hardware status register the hardware status register (hsr) gives the status of the chip after a hardware problem has been detected. table 3 register hsr (address 0fh; read only); note 1 note 1. register value at reset: all significant bits are cleared after reset, except bit supl which is set within pulse rstout. 76543210 cs7 cs6 cs5 cs4 riu sc3 sc2 sc1 bit symbol description 7 cs7 ic identi?cation . default value for identifying the ic: 0010 = tda8007bhl/c2 0011 = tda8007bhl/c3 6 cs6 5 cs5 4 cs4 3 riu reset iso uart. when reset, this bit resets a large part of the uart registers to their initial value. bit riu must be reset before any activation; logic 0 for at least 10 ns duration. bit riu must be set to logic 1 by software before any action on the uart can take place. 2 sc3 select card 3 . if bit sc3 = 1, then card 3 is selected. 1 sc2 select card 2 . if bit sc2 = 1, then card 2 is selected. 0 sc1 select card 1 . if bit sc1 = 1, then card 1 is selected. 76543210 hs7 prtl2 prtl1 supl prl2 prl1 intauxl ptl
2003 feb 18 14 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 4 description of hsr bits. bit symbol description 7 hs7 not used 6 prtl2 protection 2 . bit prtl2 = 1 when a fault has been detected on card reader 2. bit prtl 2 is the or-function of the protection on pin v cc2 and pin rst2. 5 prtl1 protection 1 . bit prtl1 = 1 when a fault has been detected on card reader 1. bit prtl 1 is the or-function of the protection on pin v cc1 and pin rst1. 4 supl supervisor latch . bit supl = 1 when the supervisor has been activated. 3 prl2 presence latch 2 . bit prl2 = 1 when a level change has occurred on pin pres2. 2 prl1 presence latch 1 . bit prl1 = 1 when a level change has occurred on pin pres1. 1 intauxl auxiliary interrupt change . bit intauxl = 1 if the level on pin intaux has been changed. 0 ptl overheating . bit ptl = 1 if overheating has occurred. when at least one of the bits prtl2, prtl1, prl2, prl1 or ptl is high, then int is low. the bits having caused the interrupt are cleared when register hsr has been read-out. the same occurs with intauxl, if not disabled. in case of an emergency deactivation (by bits prtl2, prtl1, supl, prl2, prl1 or ptl), bit start (bit 0 in the pcr) is automatically reset by hardware. at power-on, or after a supply voltage drop-out, bit supl is set and pin int = low. pin int will return to high level at the end of the alarm pulse rstout (see fig.13). bit supl will be reset only after a status register read-out outside the alarm pulse. a minimum time of 2 m s is needed between two successive read operations of register hsr, as well as between reading of register hsr and activation (write in register pcr). 8.2.1.3 time-out registers the three time-out registers (tor1, tor2 and tor3) form a programmable 24-bit etu counter, or two independant counters (one 16-bit and one 8-bit). the value to load in registers tor1, tor2 and tor3 is the number of etu to count. the time-out counters may only be used when a card is active with a running clock. table 5 register tor1 (address 09h; write only); note 1 note 1. register value at reset: all bits are cleared after reset. table 6 register tor2 (address 0ah; write only); note 1 note 1. register value at reset: all bits are cleared after reset. table 7 register tor3 (address 0bh; write only); note 1 note 1. register value at reset: all bits are cleared after reset. 76543210 tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 76543210 tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8 76543210 tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16
2003 feb 18 15 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.1.4 time-out con?guration register the time-out configuration (toc) register is used for setting different configurations of the time-out counter as given in table 9; all other configurations are undefined. table 8 register toc (address 08h; read and write); note 1 note 1. register value at reset: all bits are cleared after reset. table 9 c ard registers 76543210 toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 toc value operating mode 00h all counters are stopped. 05h counters 2 and 3 are stopped; counter 1 continues to operate in auto-reload mode. 61h counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. counting the value stored in registers tor3 and tor2 is started after 61h is written in register toc. an interrupt is given, and bit to3 is set within register usr when the terminal count is reached. the counter is stopped by writing 00h in register toc, and should be stopped before reloading new values in registers tor2 and tor3. 65h counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. counter 1 starts counting the content of register tor1 on the ?rst start bit (reception or transmission) detected on pin i/o after 65h is written in register toc. when counter 1 reaches its terminal count, an interrupt is given, bit to1 in register usr is set, and the counter automatically restarts the same count until it is stopped. it is not allowed to change the content of register tor1 during a count. counters 3 and 2 are wired as a single 16-bit counter and start counting the value in registers tor3 and tor2 when 65h is written in register toc. when the counter reaches its terminal count, an interrupt is given and bit to3 is set within register usr. both counters are stopped when 00h is written in register toc. counters 3 and 2 shall be stopped by writing 05h in register toc before reloading new values in registers tor2 and tor3. 68h counters 3, 2 and 1 are wired as a single 24-bit counter. counting the value stored in registers tor3, tor2 and tor1 is started after 68h is written in register toc. the counter is stopped by writing 00h in register toc. it is not allowed to change the content of registers tor3, tor2 and tor1 within a count. 71h counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. counting the value stored in registers tor3 and tor2 and is started on the ?rst start bit detected on pin i/o (reception or transmission) after the value has been written, and then on each subsequent start bit. it is possible to change the content of registers tor3 and tor2 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. the counter is stopped by writing 00h in register toc. in this con?guration, registers tor3, tor2 and tor1 must not be all zero. 75h counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. counter 1 starts counting the content of register tor1 on the ?rst start bit (reception or transmission) detected on pin i/o after 75h is written in register toc. when counter 1 reaches its terminal count, an interrupt is given, bit to1 in register usr is set, and the counter automatically restarts the same count until it is stopped. changing the content of register tor1 during a count is not allowed. counting the value stored in registers tor3 and tor2 is started on the ?rst start bit detected on pin i/o (reception or transmission) after the value has been written, and then on each subsequent start bit. it is possible to change the content of registers tor3 and tor2 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. the counter is stopped by writing 00h in register toc. in this con?guration, registers tor3, tor2 and tor1 must not be all zero.
2003 feb 18 16 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 7ch counters 3, 2 and 1 are wired as a single 24-bit counter. counting the value stored in registers tor3, tor2 and tor1 is started on the ?rst start bit detected on pin i/o (reception or transmission) after the value has been written, and then on each subsequent start bit. it is possible to change the content of registers tor3, tor2 and tor1 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. the counter is stopped by writing 00h in register toc. in this con?guration, registers tor3, tor2 and tor1 must not be all zero. 85h same as value 05h, except that all the counters will be stopped at the end of the 12th etu following the ?rst received start bit detected after 85h has been written in register toc. e5h same con?guration as value 65h, except that counter 1 will be stopped at the end of the 12th etu following the ?rst start bit detected after e5h has been written in register toc. f1h same con?guration as value 71h, except that the 16-bit counter will be stopped at the end of the 12th etu following the ?rst start bit detected after f1h has been written in register toc. f5h same con?guration as value 75h, except the two counters will be stopped at the end of the 12th etu following the ?rst start bit detected after f5h has been written in register toc. toc value operating mode the time-out counter is very useful for processing the clock counting during atr, the work waiting time (wwt) or the waiting times defined in protocol t = 1. it should be noted that the 200 and n max clock counter (n max = 384 for tda8007bhl/c2; n max = 368 for tda8007bhl/c3) used during atr is done by hardware when the start session is set, specific hardware controls the functionality of bgt in t = 1 and t = 0 protocols and a specific register is available for processing the extra guard time. writing to register toc is not allowed as long as the card is not activated with a running clock. before restarting the 16-bit counter (counters 3 and 2) by writing 61h, 65h, 71h, 75h, f1h or f5h in the toc; or the 24-bit counter (counters 3, 2 and 1) by writing 68h in the toc; it is mandatory to stop them by writing 00h in the toc. detailed examples of how to use these specific timers can be found in application note an01054 .
2003 feb 18 17 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.2 iso uart registers 8.2.2.1 uart transmit register table 10 register utr (address 0dh; write only); note 1 note 1. register value at reset: all bits are cleared after reset. 76543210 ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 when the microcontroller wants to transmit a character to the selected card, it writes the data in direct convention in the uart transmit register (utr). the transmission: starts at the end of writing (on the rising edge of signal wr) if the previous character has been transmitted and if the extra guard time has expired starts at the end of the extra guard time if this one has not expired does not start if the transmission of the previous character is not completed with a synchronous card (bit san within register ucr2 is set), only signal d0 is relevant and is copied on pin i/o of the selected card. 8.2.2.2 uart receive register table 11 register urr (address 0dh; read only); note 1 note 1. register value at reset: all bits are cleared after reset. 76543210 ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 when the microcontroller wants to read data from the card, it reads it from the uart receive register (urr) in direct convention: with a synchronous card, only d0 is relevant and is a copy of the state of the selected card i/o when needed, this register may be tied to a fifo whose length n is programmable between 1 and 8; if n > 1, then no interrupt is given until the fifo is full and the controller may empty the fifo when required with a parity error: C in protocol t = 0; the received byte is not stored in the fifo and the error counter is incremented. the error counter is programmable between 1 and 8. when the programmed number is reached, then the bit pe is set in the status register usr and int0 falls low. the error counter must be reprogrammed to the desired value after its count has been reached C in protocol t = 1; the character is loaded in the fifo and the bit pe is set whatever the programmed value in the parity error counter when the fifo is full, then the bit rbf in the status register usr is set. this bit is reset when at least one character has been read from urr when the fifo is empty, then the bit fe is set in the status register usr as long as no character has been received. 8.2.2.3 mixed status register the mixed status register (msr) relates the status of pin intaux, the cards presence contacts pres1 and pres2, the bgt counter, the fifo empty indication and the transmit or receive ready indicator tbe/rbf. it also gives useful indications when switching the clock to or from 1 / 2 f int and when driving the tda8007bhl/c with fast controllers. no bits within register msr act upon signal int.
2003 feb 18 18 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 12 register msr (address 0ch; read only); note 1 note 1. register value at reset: bits tbe/rbf, bgt and clksw are cleared after reset; bits fe and cred are set after reset. table 13 description of msr bits. 76543210 clksw fe bgt cred pr2 pr1 intaux tbe/rbf bit symbol description 7 clksw clock switch . bit clksw is set when the tda8007bhl/c has performed a required clock switch from 1 n f xtal to 1 2 f int , and is reset when the tda8007bhl/c has performed a required clock switch from 1 2 f int to 1 n f xtal . the application must wait until this bit is set or reset before sending a new command to the card. this bit is reset at power-on. 6fe fifo empty . bit fe is set when the reception fifo is empty. it is reset when at least one character has been loaded in the fifo. 5 bgt block guard time . in protocol t = 1, bit bgt is linked with a 22-etu counter which is started at every start bit on pin i/o. bit bgt is set if the count is ?nished before the next start bit. this helps to verify that the card has not answered before 22 etu after the last transmitted character, or that the reader is not transmitting a character before 22 etu after the last received character. in protocol t = 0, bit bgt is linked with a 16-etu counter which is started at every start bit on pin i/o. bit bgt is set if the count is ?nished before the next start bit. this helps to verify that the reader is not transmitting a character before 16 etu after the last received character. 4 cred control ready . it is advised bit cred is used for driving the tda8007bhl/c with high speed controllers. before writing in registers toc or utr, or reading from register urr, check if bit cred is set. if reset, it means that the writing or reading operation will not be correct because the controller is acting faster than the required time for this operation: 3 clock cycles after rising edge rd for reading from register urr: t rd(urr) - t w(rd) (see fig.9). 3 clock cycles after rising edge wr for writing in register utr: t wr(utr) - t w(wr) (see fig.10) 3 31 or 3 32 etu after rising edge wr for writing in register toc: t wr(toc) - t w(wr) (see fig.11) bit cred is set at power-on. 3 pr2 card 2 present . bit pr2 = 1 when card 2 is present. 2 pr1 card 1 present . bit pr1 = 1 when card 1 is present. 1 intaux auxiliary interrupt . bit intaux is set when pin intaux = high and it is reset when pin intaux = low. 0 tbe/rbf transmit buffer empty/receive buffer full . bit tbe/rbf = 1 when: changing from reception mode to transmission mode a character has been transmitted by the uart the reception fifo is full. bit tbe/rbf = 0 after power-on or after one of the following: when bit riu is reset when a character has been written to register utr when at least one character has been read in the fifo when changing from transmission mode to reception mode.
2003 feb 18 19 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth i/o bit rbf bit fe fce903 int rd bit cred t sb(fe) t sb(rbf) t rd(urr) t rd(urr) t w(rd) fig.9 minimum time between two read operations in register urr. handbook, full pagewidth i/o bit tbe fce902 int wr bit cred t w(wr) t wr(utr) fig.10 minimum time between two write operations in register utr.
2003 feb 18 20 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b handbook, full pagewidth fce904 wr bit cred t w(wr) t wr(toc) fig.11 minimum time between two write operations in register toc.
2003 feb 18 21 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.2.4 fifo control register the fifo control register (fcr) relates the parity error count and the fifo length. table 14 register fcr (address 0ch; write only); note 1 note 1. register value at reset: all relevant bits are cleared after reset. table 15 description of fcr bits. 76543210 fc7 pec2 pec1 pec0 fc3 fl2 fl1 fl0 bit symbol description 7 fc7 not used 6 pec2 parity error count . bits pec2, pec1 and pec0 determine the number of allowed repetitions in 5 pec1 reception or in transmission before setting bit pe in register usr and pulling pin int to low level. 4 pec0 the value 000 indicates that, if only one parity error has occurred, bit pe is set; the value 111 indicates that bit pe will be set after 8 parity errors. in protocol t = 0: if a correct character is received before the programmed error number is reached, the error counter will be reset if the programmed number of allowed parity errors is reached, bit pe in register usr will be set as long as register usr has not been read if a transmitted character has been nak by the card, then the tda8007bhl/c will automatically re-transmit it a number of times equal to the value programmed in bits pec2, pec1 and pec0; the character will be resent at 15 etu in transmission mode, if bits pec2, pec1 and pec0 are logic 0, then the automatic re-transmission is invalidated; the character manually rewritten in register utr will start at 13.5 etu. in protocol t = 1: the error counter has no action: bit pe is set at the ?rst incorrectly received character. 3 fc3 not used 2 fl2 fifo length . bits fl2, fl1 and fl0 determine the depth of the fifo: 1 fl1 000 = length 1 111 = length 8. 0 fl0 8.2.2.5 uart status register the uart status register (usr) is used by the microcontroller to monitor the activity of the iso uart and that of the time-out counter. if any of the status bits fer, ovr, pe, ea, to1, to2 or to3 are set, then signal int = low. the bit having caused the interrupt is reset 2 m s after the rising edge of signal rd during a read operation of register usr. if bit tbe/rbf is set and if the mask bit distbe/rbf within register ucr2 is not set, then also signal int = low. bit tbe/rbf is reset 3 clock cycles after data has been written in register utr, or 3 clock cycles after data has been read from register urr, or when changing from transmission mode to reception mode. in order to avoid counting these clock cycles, bit cred (described in register msr) may be used. if lct mode is used for transmitting the last character, then bit tbe is not set at the end of the transmission.
2003 feb 18 22 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 16 register usr (address 0eh; read only); note 1 note 1. register value at reset: all bits are cleared after reset. table 17 description of usr bits. note 1. n max = 384 for tda8007bhl/c2; n max = 368 for tda8007bhl/c3. 76543210 to3 to2 to1 ea pe ovr fer tbe/rbf bit symbol description 7to3 time-out counter 3 . bit to3 is set when counter 3 has reached its terminal count. 6to2 time-out counter 2 . bit to2 is set when counter 2 has reached its terminal count. 5to1 time-out counter 1 . bit to1 is set when counter 1 has reached its terminal count. 4ea early answer is high if the ?rst start bit on the i/o during atr has been detected between the ?rst 200 and n max (1) clock pulses with rst low (all activities on the i/o during the ?rst 200 clock pulses with rst low are not taken into account) and before the ?rst n max (1) clock pulses with rst high. these two features are re-initialized at each toggling of rst 3pe parity error . in protocol t = 0, bit pe = 1 if the uart has detected a number of received characters with parity errors equal to the number written in bits pec2, pec1 and pec0 or if a transmitted character has been nak by the card a number of times equal to the value programmed in bits pec2, pec1 and pec0. it is set at 10.5 etu in the reception mode and at 11.5 etu in the transmission mode. in protocol t = 0, a character received with a parity error is not stored in register fifo (the card should repeat this character). in protocol t = 1, a character with a parity error is stored in the fifo and the parity error counter is not active. 2ovr overrun . bit ovr = 1 if the uart has received a new character whilst register fifo was full. in this case, at least one character has been lost. 1 fer framing error . bit fer = 1 when pin i/o was not in the high-impedance state at 10.25 etu after a start bit. it is reset when register usr has been read-out. 0 tbe/rbf transmission buffer empty/reception buffer full . bits tbe and rbf share the same bit within register usr: when in transmission mode the relevant bit is tbe; when in reception mode it is rbf. bit tbe = 1 when the uart is in transmission mode and when the microcontroller may write the next character to transmit in register utr. it is reset when the microcontroller has written data in the transmit register or when bit t/r within register ucr1 has been reset either automatically or by software. after detection of a parity error in transmission, it is necessary to wait 13.5 etu before rewriting the character which has been nak by the card. (manual mode, see table 15). bit rbf = 1 when register fifo is full. the microcontroller may read some of the characters in register urr, which clears bit rbf.
2003 feb 18 23 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.3 c ard registers when cards 1, 2 or 3 are selected, the following registers may be used for programming some specific parameters. 8.2.3.1 programmable divider register the programmable divider registers (pdr1, pdr2 and pdr3) are used for counting the cards clock cycles forming the etu (see fig.12). these are auto-reload 8-bit counters. table 18 registers pdr1, pdr2 and pdr3 (address 02h; read and write); note 1 note 1. register value at reset: all bits are cleared after reset. 8.2.3.2 uart con?guration register 2 the uart configuration registers 2 (ucr12, ucr22 and ucr32) relate the uart configuration. table 19 registers ucr12, ucr22 and ucr32 (address 03h; read and write); note 1 note 1. register value at reset: all relevant bits are cleared after reset. 76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 7 6543210 uc27 distbe/rbf disaux pdwn san a ut oconv cku psc handbook, full pagewidth programmable divider register (1 to 256) prescaler (31 or 32) multiplexer f clk 2f clk bit cku fce905 etu fig.12 elementary time unit (etu) generation.
2003 feb 18 24 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 20 description of ucr2 bits. bit symbol description 7 uc27 not used 6 distbe/rbf disable tbe/rbf interrupt bit . if bit distbe/rbf = 1, then reception or transmission of a character will not generate an interrupt. this feature is useful for increasing communication speed with the card; in this case, a copy of the bit tbe/rbf within register msr must be polled (and not the original) in order not to lose priority interrupts which can occur in register usr. 5 disaux disable auxiliary interrupt . if bit disaux in register ucr2 is set, then a change on pin intaux will not generate an interrupt, but bit intauxl will be set. therefore, it is necessary to read register hsr before bit disaux is to be reset to avoid an interrupt by bit intauxl. in order to avoid an interrupt during a change of card, it is better to set bit disaux in register ucr2 for all cards. 4pdwn power-down mode . if bit pdwn is set by software, the crystal oscillator is stopped. this mode allows low power consumption in applications where this is required. during the power-down mode, it is not possible to select a card other than the one currently selected. there are ?ve ways of escaping from the power-down mode: insert card 1 or card 2 withdraw card 1 or card 2 select the tda8007bhl/c by resetting bit cs (this assumes that the tda8007bhl/c had been deselected after setting power-down mode) bit intauxl has been set due to a change on pin intaux if pin cs = low permanently, reset bit pdwn by software. after any of these events, the tda8007bhl/c will leave the power-down mode. except in the case of a read operation of register hsr, signal int will be pulled to low level. the system microcontroller may then read the status registers after 5 ms, and signal int will return to high level (if the system microcontroller has woken the tda8007bhl/c by re-selecting it, then no bits will be set in the status registers). note that the power-down mode can only be entered if bit supl has been cleared. 3 san synchronous/asynchronous card . bit san = 1 by software if a synchronous card is expected. the uart is then bypassed and only bit 0 in registers urr and utr is connected to pin i/o. in this case the clock is controlled by bit sc in register ccr. 2 a ut oconv auto convention . if bit a ut oconv = 1, then the convention is set by software using bit conv in register ucr1. if the bit is reset, then the configuration is automatically detected on the first received character whilst the start session (bit ss) is set. bit a ut oconv must not be changed during a card session. 1 cku clock uart . for baud rates other than those given in table 21, there is the possibility to set bit cku = 1. in this case, the etu will last half the number of card clock cycles equal to prescaler pdrx. note that bit cku = 1 has no effect if f clk =f xtal . this means, for example, that 76800 baud is not possible when the card is clocked with the external frequency on pin xtal1. 0 psc prescale select . if bit psc = 1, then the prescaler value is 32. if bit psc = 0, then the prescaler value is 31. one etu will last a number of cards clock cycles equal to prescaler pdrx. all baud rates specified in the iso 7816 norm are achievable with this configuration (see table 21).
2003 feb 18 25 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 21 baud rate selection using values f and d; card clock frequency f clk = 3.58 mhz for psc = 31 and f clk = 4.92 mhz for psc = 32 (example; in the table 31;12 means prescaler set to 31 and pdr set to 12) 8.2.3.3 guard time register the guard time registers (gtr1, gtr2 and gtr3) are used for storing the number of guard etu given by the card during atr. in transmission mode, the uart will wait this number of etu before transmitting the character stored in register utr. when register gtrx = ff: in protocol t = 1 C tda8007bhl/c2 operates at 11 etu C tda8007bhl/c3 operates at 10.8 etu in protocol t = 0 C tda8007bhl/c2 operates at 12 etu C tda8007bhl/c3 operates at 11.8 etu. table 22 registers gtr1, gtr2 and gtr3 (address 05h; read and write); note 1 note 1. register value at reset: all bits are cleared after reset. d f 0 123456910111213 1 31;12 9600 31;12 9600 31;18 6400 31;24 4800 31;36 3200 31;48 2400 31;60 1920 32;16 9600 32;24 6400 32;32 4800 32;48 3200 32;64 2400 2 31;6 19200 31;6 19200 31;9 12800 31;12 9600 31;18 6400 31;24 4800 31;30 3840 32;8 19200 32;12 12800 32;16 9600 32;24 6400 32;32 4800 3 31;3 38400 31;3 38400 31;6 19200 31;9 12800 31;12 9600 31;15 7680 32;4 38400 32;6 25600 32;8 19200 32;12 12800 32;16 9600 4 31;3 38400 31;6 19200 32;2 76800 32;3 51300 32;4 38400 32;6 25600 32;8 19200 5 31;3 38400 32;1 153600 32;2 76800 32;3 51300 32;4 38400 6 32;1 153600 32;2 76800 8 31;1 115200 31;1 115200 31;2 57600 31;3 38400 31;4 28800 31;5 23040 32;2 76800 32;4 38400 9 31;3 38400 76543210 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0
2003 feb 18 26 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.3.4 uart con?guration register 1 the uart configuration registers 1 (ucr11, ucr21 and ucr31) set the parameters of the iso uart. table 23 registers ucr11, ucr21 and ucr31 (address 06h; read and write); note 1 note 1. register value at reset: all relevant bits are cleared after reset. table 24 description of ucr1 bits 8.2.3.5 clock con?guration registers the clock configuration registers (ccr1, ccr2 and ccr3) relate the clock signals: for cards 1 and 2, register ccrx defines the clock for the selected card for cards 1, 2 and 3, register ccrx defines the clock to the iso uart. it should be noted that, if bit cku in the prescaler register of the selected card (register ucr2) is set, then the iso uart is clocked at twice the frequency of the card, which allows baud rates not foreseen in iso 7816 norm to be reached. table 25 registers ccr1, ccr2 and ccr3 (address 01h; read and write); note 1 note 1. register value at reset: all relevant bits are cleared after reset. 76543210 uc17 fip fc prot t/r lct ss conv bit symbol description 7 uc17 not used 6 fip force inverse parity . if bit fip is set to logic 1, the uart will nak a correctly received character, and will transmit characters with wrong parity bits. 5fc test . bit fc is a test bit, and must be left at logic 0. 4prot protocol . bit prot is set if the protocol is t = 1 (asynchronous) and bit prot = 0 if the protocol is t=0. 3 t/r transmit/receive . bit t/r is set by software for transmission mode. a change from logic 0 to 1 will set bit tbe in register usr. bit t/r is automatically reset by hardware if bit lct has been used before transmitting the last character. 2 lct last character to transmit . bit lct is set by software before writing the last character to be transmitted in the utr. it allows automatic change to reception mode. it is reset by hardware at the end of a successful transmission. when lct is being reset, the bit t/r is also reset and the iso 7816 uart is ready for receiving a character. 1ss software convention setting . bit ss is set by software before atr for automatic convention detection and early answer detection. it is automatically reset by hardware at 10.5 etu after reception of the initial character. 0 conv convention . bit conv is set if the convention is direct. bit conv is either automatically written by hardware according to the convention detected during atr, or by software if the bit a ut oconv in register ucr2x is set. 76543210 cc7 cc6 shl cst sc ac2 ac1 ac0
2003 feb 18 27 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b table 26 description of ccrx bits clock switching constraints: f int is the frequency delivered by the internal oscillator in case of f clk =f xtal , the duty cycle must be ensured by the incoming clock signal on pin xtal1 when switching from 1 n f xtal to 1 2 f int or vice verse, only bit ac2 must be changed (bits ac1 and ac0 must remain the same). when switching from 1 n f xtal or 1 2 f int to clock stopped or vice verse, only bits cst and shl must be changed when switching from 1 n f xtal to 1 2 f int or vice verse, a delay can occur between the command and the effective frequency change on clk (the fastest switching time is from 1 2 f xtal to 1 2 f int or vice verse, the best for duty cycle is from 1 8 f xtal to 1 2 f int or vice verse) it is necessary to survey the bit clksw in register msr before re-transmitting commands to the card. bit symbol description 7 cc7 not used 6 cc6 not used 5 shl stop high or low . if bit cst = 1, then the clock is stopped at low level if bit shl = 0, and at high level if bit shl = 1. 4 cst clock stop . in the case of an asynchronous card, bit cst de?nes whether the clock to the card is stopped or not; if bit cst is reset, then the clock is determined by bits ac0, ac1 and ac2. 3sc synchronous clock . in the event of a synchronous card, then contact clk is the copy of the value of bit sc; in reception mode, the data from the card is available to bit ur0 after a read operation of register urr; in transmission mode, the data is written on the i/o line of the card when register utr has been written to and remains unchanged when another card is selected. 2to0 ac alternating clock . all frequency changes are synchronous, thus ensuring that no spikes or unwanted pulse widths occur during changes. ac2 ac1 ac0 clock frequencies (asynchronous card) 000 f xtal 001 1 2 f xtal 010 1 4 f xtal 011 1 8 f xtal 100 1 2 f int 101 110 111
2003 feb 18 28 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.3.6 power control registers the power control registers (pcr1 and pcr2): start or stop card sessions read from or write to auxiliary card contacts c4 and c8 are available only for cards 1 or 2. to deactivate the card, only bit start should be reset. table 27 registers pcr1 and pcr2 (address 07h; read and write) note 1. register value at reset: all relevant bits are cleared after reset. table 28 description of pcrx bits 76543210 pcr7 pcr6 c8 c4 1v8 rstin 3v/5v start bit symbol description 7 pcr7 not used 6 pcr6 not used 5c8 contact 8 . when writing to register pcr, pin c8 will output the value of bit c8. when reading from register pcr, bit c8 will store the value on pin c8. 4c4 contact 4 . when writing to register pcr, pin c4 will output the value of bit c4. when reading from register pcr, bit c4 will store the value on pin c4. 3 1v8 1.8 v cards . if bit 1v8 is set, then v cc = 1.8 v: it should be noted that no speci?cation is guaranteed with this v cc voltage when the supply voltage v dd is inferior to 3 v 2 rstin reset bit . when the card is activated, pin rst is the copy of the value written in bit rstin. 1 3v/5v 3 or 5 v cards . if bit 3v/5v = 1, then v cc = 3 v; if bit 3v/5v = 0, then v cc =5v. 0start start . if the microcontroller sets bit start = 1, then the selected card is activated (see section 8.6); if the microcontroller resets bit start = 0, then the card is deactivated (see section 8.7). bit start is automatically reset in case of emergency deactivation. to deactivate the card, only bit start should be reset.
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2003 feb 18 29 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.2.4 r egister summary table 29 register summary notes 1. registers pdr, gtr, ucr1, ucr2, ccr and pcr vary according to the card selected. 2. x = undefined; u = no change. 3. tda8007bhl/c2: v = 0; tda8007bhl/c3: v = 1. addr name r/w 7 6 5 43210 value at reset (2) value when riu=0 (2) 00 csr (1) r/w 0 0 1 0 riu sc3 sc2 sc1 001v 0000 (3) 001v 0000 (3) 01 ccr (1) r/w not used not used shl cst sc ac2 ac1 ac0 xx00 0000 xxuu uuuu 02 pdr (1) r/w pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0000 0000 uuuu uuuu 03 ucr2 (1) r/w not used distbe/ rbf disaux pdwn san a ut oc cku psc x000 0000 uuuu uuuu 05 gtr (1) r/w gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 0000 0000 uuuu uuuu 06 ucr1 (1) r/w not used fip fc prot t/r lct ss conv x000 0000 xuuu 00uu 07 pcr (1) r/w not used not used c8 c4 1v8 rstin 3v/5v start xx11 0000 xx11 uuuu 08 toc r/w toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 0000 0000 0000 0000 09 tor1 w tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 0000 0000 uuuu uuuu 0a tor2 w tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8 0000 0000 uuuu uuuu 0b tor3 w tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16 0000 0000 uuuu uuuu 0c msr r clksw fe bgt cred pr2 pr1 intaux tbe/rbf 0101 xxx0 u1u1 uuu0 0c fcr w not used pec2 pec1 pec0 not used fl2 fl1 fl0 x000 x000 xuuu xuuu 0d urr r ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 0000 0000 0000 0000 0d utr w ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 0000 0000 0000 0000 0e usr r to3 to2 to1 ea pe ovr fer tbe/rbf 0000 0000 0000 0000 0f hsr r not used prtl2 prtl1 supl prl2 prl1 intauxl ptl x001 0000 xuuu xxxu
2003 feb 18 30 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.3 supplies and voltage supervisor the tda8007bhl/c operates within a supply voltage range of 2.7 to 6 v. the supply pins are v dd , v dda , gnd and agnd. pins v dda and agnd supply the analog drivers to the cards and have to be decoupled externally because of the large current spikes that the cards and the step-up converter can create. v dda may be different from v dd . pins v dd and gnd supply the remainder of the chip. an integrated spike killer ensures that the contacts to the cards remain inactive during power-up and power-down. an internal voltage reference is generated for use within the step-up converter, the voltage supervisor and the v cc generators. the voltage supervisor generates an alarm pulse when v dd is too low to ensure proper operation. the alarm pulse length is defined by an external capacitor tied to pin delay and is typically 1 ms per 2 nf. the alarm pulse may be used as a reset pulse by the system microcontroller (pin rstout = high). it can also be used to block any spurious noise on card contacts during the microcontrollers reset, or to force an automatic deactivation of the contacts in the event of a supply drop-out (see sections 8.6 and 8.7). after power-on, or after a voltage drop, bit supl is set within register hsr and remains set until register hsr is read-out outside the alarm pulse. signal int = low for the duration that signal rstout is active. handbook, full pagewidth v th1 v dd v th2 cdelay rstout supl int supply dropout power-off reset by c delay power-on status read fce683 t w fig.13 voltage supervisor.
2003 feb 18 31 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.4 step-up converter except for the v cc generator and the other cards contact buffers, the whole circuit is powered by v dd and v dda . if the supply voltage is 2.5 v, then a higher voltage is needed for the iso contacts supply. when a card session is requested by the microcontroller, the sequencer first enables the step-up converter (switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 mhz. supposing that v cc is the maximum of v cc1 and v cc2 , then the possible situations are: v cc =5v C for v dd = 3 v the step-up converter acts as a voltage tripler with regulation of v up at approximately 5.5 v C for v dd = 5 v the step-up converter acts as a voltage doubler with regulation of v up at approximately 5.5 v v cc =3v C for v dd = 3 v the step-up converter acts as a voltage doubler with regulation of v up at approximately 4.0 v C for v dd = 5 v the step-up converter acts as a voltage follower and v dd is applied to v up v cc = 1.8 v C the step-up converter acts as a voltage follower for any value of v dd . the recognition of the supply voltage is done by the tda8007bhl/c at approximately 3.5 v. the output voltage v up is fed to the v cc generators. v cc and cgnd are used as a reference for all other card contacts. 8.5 iso 7816 security the correct sequence during activation and deactivation of the cards is ensured by two specific sequencers, the clock is defined by a division ratio of the internal oscillator. activation (bit start = 1 in registers pcr1 or pcr2) is only possible if the card is present (pin pres is active high with an internal current source to ground) and if the supply voltage is correct (voltage supervisor not active). the presence of the cards is signalled to the microcontroller by register hsr. bits pr1 or pr2 in register msr are set if card 1 or 2 is present. bits prl1 or prl2 are set if pins pres1 or pres2 have been toggled. during a session, the sequencer performs an automatic emergency deactivation on one card in the event of card take-off, or short-circuit. both cards are automatically deactivated in the event of a supply voltage drop, or overheating. register hsr is updated and the int line falls so that the system microcontroller is aware of what happened.
2003 feb 18 32 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.6 activation sequence when the cards are inactive, pins v cc , clk, rst, c4, c8 and i/o are at low level and have a low-impedance with respect to ground. the step-up converter is stopped. when everything is satisfactory (voltage supply, card present and no hardware problems), the system microcontroller may initiate an activation sequence of a present card. after selecting the card and leaving the uart reset mode, and then configuring the necessary parameters for the counters and the uart, bit start can be set within register pcr at t 0 (see fig.14): 1. the step-up converter is started (t 1 ); if one card was already active, then the step-up converter was already on and nothing more occurs at this step. 2. pin v cc starts rising (t 2 ) from 0 to 3 or 5 v with a controlled rise time of 0.17 v/ m s (typical). 3. pin i/o rises to v cc (t 3 ); pins c4 and c8 also rise if bits c4 and c8 within register pcr have been set to logic 1 (integrated 14 k w pull-up resistors to v cc ). 4. clock pulse clk is sent to the card (t 4 ) and pin rst is enabled. 5. after a number of clk pulses that can be counted with the time-out counter, bit rstin may be set by software and pin rst will then rise to v cc . 6. the sequencer is clocked by 1 64 f int which leads to a time interval of t = 25 m s (typical). thus: t 1 =0to 1 64 t t 2 =t 1 + 3 2 t t 3 =t 1 + 7 2 t t 4 =t 1 + 4t. handbook, full pagewidth start v up v cc i/o rstin clk rst t 0 t 2 t 3 t 4 = t act at r t 1 fce684 fig.14 activation sequence.
2003 feb 18 33 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 8.7 deactivation sequence when the session is completed, the microcontroller resets bit start at t 10 . the circuit then executes an automatic deactivation sequence (see fig.15): 1. the card is reset by signal rst = low (t 11 ). 2. clock pulse clk is stopped (t 12 ). 3. pins i/o, c4 and c8 fall to 0 v (t 13 ). 4. pin v cc falls to 0 v with typical 0.17 v/ m s slew rate (t 14 ). 5. the step-up converter is stopped (t 15 ) and pins clk, rst, v cc and i/o become low-impedance to ground, if both cards are inactive. thus: t 11 =t 10 + 1 64 t t 12 =t 11 + 1 2 t t 13 =t 11 +t t 14 =t 11 + 3 2 t t 15 =t 11 + 7 2 t t de = time that v cc needs to decrease to less than 0.4 v. handbook, full pagewidth start v up v cc i/o clk rst t 10 t 12 t 13 t de t 14 t 15 t 11 fce685 fig.15 deactivation sequence.
2003 feb 18 34 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 9 limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. human body model as defined in jedec standard jesd22-a114-b, dated june 2000. 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. 11 thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v dda analog supply voltage - 0.5 +6.5 v v n input voltage on pins sam, sap, sbm, sbp and v up - 0.5 +7.5 v on all other pins - 0.5 v dd + 0.5 v p tot total power dissipation t amb = - 25 to +85 c - 700 mw t stg storage temperature - 55 +150 c t j junction temperature - 125 c v es electrostatic discharge voltage human body model; note 1 on pins i/o1, i/o2, v cc1 ,v cc2 , rst1, rst2, clk1, clk2, cgnd1, cgnd2, pres1 and pres2 - 6+6 kv on pins c41, c42, c81 and c82 - 5+5 kv on all other pins - 2+2 kv symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 78 k/w
2003 feb 18 35 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 12 characteristics v dd = 3.3 v; v dda = 3.3 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 2.7 - 6.0 v v dda supply voltage for step-up converter v dd - 6.0 v i dd(pd) supply current in power-down mode cards inactive; f xtal =0hz -- 350 m a cards active; v cc =5v; f clk = 0 hz; f xtal =0hz -- 3ma i dd(sm) supply current in sleep mode cards active; f clk =0hz -- 5.5 ma i dd(oper) supply current in operating modem 5 v cards i cc1 = 65 ma; i cc2 = 15 ma; f xtal = 20 mhz; f clk = 10 mhz; v dd = 2.7 v -- 315 ma 3 v cards i cc1 = 50 ma; i cc2 = 30 ma; f xtal = 20 mhz; f clk =10mhz v dd = 2.7 v -- 215 ma v dd =5v -- 100 ma voltage supervisor; see fig.13 v th1 threshold voltage on pin v dd falling 2.10 - 2.50 v v hys1 hysteresis on v th1 50 - 170 mv c apacitor connection : pin delay v th2 threshold voltage - 1.25 - v v o output voltage -- v dd + 0.3 v i o output current v delay = 0 v (charge) -- 2 -m a v delay =v dd (discharge) - 2 - ma c o output capacitance 1 -- nf t w alarm pulse width c delay =22nf - 10 - ms o utput : pin rstout (open-drain output) active high option v oh high-level output voltage i oh = - 1 ma 0.8v dd - v dd + 0.3 v i ol low-level output current v ol =0v --- 10 m a active low option i oh high-level output current v oh =5v -- 10 m a v ol low-level output voltage i ol =2ma - 0.3 - +0.4 v
2003 feb 18 36 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b crystal oscillator f xtal crystal frequency 4 - 20 mhz f ext external frequency on pin xtal1 0 - 20 mhz step-up converter f int internal oscillator frequency 2 2.5 3.7 mhz v vup voltage on pin v up at least one 5 v card - 5.7 - v both 3 v cards - 4.1 - v v det(dt) detection voltage on pin v dd for doubler or tripler selection 3.4 3.5 3.6 v reset output to the cards: pins rst1 and rst2 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i o(inactive) = 1 ma 0 - 0.3 v i o(inactive) output current in inactive mode v o =0v 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.5 - v cc v t r rise time c l =30pf -- 0.1 m s t f fall time c l =30pf -- 0.1 m s clock output to the cards: pins clk1 and clk2 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i o(inactive) = 1 ma 0 - 0.3 v i o(inactive) output current in inactive mode v o =0v 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.5 - v cc v t r rise time c l =30pf -- 8ns t f fall time c l =30pf -- 8ns f clk clock frequency idle con?guration (1 mhz) 1 - 1.85 mhz operational 0 - 10 mhz d duty factor c l =30pf 45 - 55 % sr slew rate (rise and fall) c l =30pf 0.2 -- v/ns card supply output voltage: pins v cc1 and v cc2 ; note 1 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i o(inactive) = 1 ma 0 - 0.3 v i o(inactive) output current in inactive mode v o =0v --- 1ma symbol parameter conditions min. typ. max. unit
2003 feb 18 37 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b v cc output voltage in active mode 5 v card; i cc < 65 ma 4.75 5 5.25 v 3 v card; i cc < 50 ma 2.78 3 3.22 v 1.8 v card; i cc < 30 ma 1.65 1.8 1.95 v 5 v card; current pulses of 40 nc with i < 200 ma, t < 400 ns and f < 20 mhz 4.6 - 5.4 v 3 v card; current pulses of 24 nc with i < 200 ma, t < 400 ns and f < 20 mhz 2.75 - 3.25 v 1.8 v card; current pulses of 12 nc with i < 200 ma, t < 400 ns and f < 20 mhz 1.62 - 1.98 v i cc output current 5 v card; v cc =0to5v --- 65 ma 3 v card; v cc =0to3v --- 50 ma 1.8 v card; v cc = 0 to 1.8 v --- 30 ma i cc1 +i cc2 sum of both output currents --- 80 ma sr slew rate up or down; maximum capacitance of 300 nf 0.05 0.16 0.22 v/ m s data lines: pins i/o1 and i/o2; note 2 r pu internal pull-up resistance between pin i/o and v cc 11 14 17 k w v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i o(inactive) =1ma -- 0.3 v i o(inactive) output current in inactive mode v o =0v --- 1ma con?gured as output v ol low-level output voltage i ol =1ma 0 - 0.3 v v oh high-level output voltage i oh < - 20 m a 0.8v cc - v cc + 0.25 v i oh < - 40 m a for 5 and 3 v cards 0.75v cc - v cc + 0.25 v t o(r) , t o(f) output transition time (rise and fall time) c l 30 pf -- 0.1 m s con?gured as input v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 1.5 - v cc v i il low-level input current v il =0v -- 600 m a i lih high-level input leakage current v ih =v cc -- 20 m a t i(r) , t i(f) input transition time (rise and fall time) c l 30 pf -- 1.2 m s symbol parameter conditions min. typ. max. unit
2003 feb 18 38 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b auxiliary cards contacts: pins c41, c81, c42 and c82; note 3 v o(inactive) output voltage in inactive mode no load 0 - 0.1 v i o(inactive) =1ma -- 0.3 v i o(inactive) output current in inactive mode v o =0v --- 1ma t w(pu) active pull-up pulse width - 200 - ns r int(pu) internal pull-up resistance between pins c4 or c8 and v cc 81012k w f max maximum frequency on card contact pins -- 1 mhz con?gured as output v ol low-level output voltage i ol =1ma 0 - 0.3 v v oh high-level output voltage i oh < - 20 m a 0.8v cc - v cc + 0.25 v i oh < - 40 m a for 5 and 3 v cards 0.75v cc - v cc + 0.25 v t o(r) , t o(f) output transition time (rise and fall time) c l =30pf -- 0.1 m s con?gured as input v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 1.5 - v cc v i il low-level input current v il =0v -- 600 m a i lih high-level input leakage current v ih =v cc -- 20 m a t i(r) , t i(f) input transition time (rise and fall time) c l =30pf -- 1.2 m s timing t act activation sequence duration see fig.14 -- 130 m s t de deactivation sequence duration see fig.15 -- 150 m s protection and limitation i cc(sd) shutdown and limitation current at pin v cc -- 100 - ma i i/o(lim) limitation current on pin i/o - 15 - +15 ma i clk(lim) limitation current on pin clk - 70 - +70 ma i rst(sd) shutdown current on pin rst -- 20 - ma i rst(lim) limitation current on pin rst - 20 - +20 ma t sd shutdown temperature - 150 - c symbol parameter conditions min. typ. max. unit
2003 feb 18 39 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b card presence inputs: pins pres1 and pres2 v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i lil low-level input leakage current v il =0v -- 40 m a i lih high-level input leakage current v ih =v dd -- 40 m a bidirectional data bus: pins d0 to d7 con?gured as input v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i lil low-level input leakage current - 20 - +20 m a i lih high-level input leakage current - 20 - +20 m a c l load capacitance -- 10 pf con?gured as output v ol low-level output voltage i ol =5ma -- 0.2v dd v v oh high-level output voltage i oh = - 5 ma 0.8v dd -- v t o(r) , t o(f) output transition time (rise and fall time) c l =50pf -- 25 ns logic inputs: pins ale, ad0, ad1, ad2, ad3, intaux, cs, rd and wr v il low-level input voltage - 0.3 - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.3 v i lil low-level input leakage current - 20 - +20 m a i lih high-level input leakage current - 20 - +20 m a c l load capacitance -- 10 pf auxiliary input and output: pin i/oaux; note 4 r int(pu) internal pull-up resistance between pin i/oaux and v dd 11 14 17 k w f max maximum frequency on pin i/oaux -- 1 mhz con?gured as input v il low-level input voltage - 0.3 - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.3 v i lih high-level input leakage current - 20 - +20 m a i il low-level input current v il =0v --- 600 m a t i(r) , t i(f) input transition time (rise and fall time) c l =30pf -- 1.2 m s symbol parameter conditions min. typ. max. unit
2003 feb 18 40 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b notes 1. to meet these specifications, two ceramic multilayer capacitors with low esr of minimum 100 nf should be used. 2. pin i/o1 has an integrated 14 k w pull-up resistance to v cc1 and pin i/o2 has an integrated 14 k w pull-up resistance to v cc2 . 3. pins c41 and c81 have an integrated 10 k w pull-up resistance to v cc1 and pins c42 and c82 have an integrated 10 k w pull-up resistance to v cc2 . 4. pin i/oaux has a 14 k w pull-up resistance to v dd . 13 timing v dd = 3.3 v; v dda = 3.3 v; t amb =25 c; unless otherwise speci?ed. con?gured as output v ol low-level output voltage i ol =1ma -- 300 mv v oh high-level output voltage i oh =40 m a 0.75v dd - v dd + 0.25 v t o(r) , t o(f) output transition time (rise and fall time) c l =30pf -- 0.1 m s interrupt line: pin int (open-drain output) v oh low-level output voltage i oh =2ma -- 0.3 v i lih high-level input leakage current -- 10 m a symbol parameter conditions min. typ. max. unit timing for multiplexed bus; see fig.4 t cy(xtal1) xtal1 cycle time 50 -- ns t w(ale) ale pulse width 20 -- ns t avll address valid to ale low 10 -- ns t (al - rwl) ale low to rd or wr low 10 -- ns t w(rd) rd pulse width for register urr 2t cy(xtal1) -- ns for other registers 10 -- ns t (rl - dv) rd low to data read valid -- 50 ns t (rwh - ah) rd or wr high to ale high 10 -- ns t w(wr) wr pulse width 10 -- ns t (dv - wl) data write valid to wr low 10 -- ns timing for non-multiplexed bus r ead control ; see fig.5 t 1 rd high to cs low 10 -- ns t 2 access time cs low to data out valid -- 50 ns t 3 cs high to data out high-impedance -- 10 ns symbol parameter conditions min. typ. max. unit
2003 feb 18 41 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b note 1. psc is the programmed prescaler value (31 or 32). w rite control ; see figs 6 and 7 t 4 data valid to end-of-write 10 -- ns t 5 data hold time 10 -- ns t 6 rd low to cs or wr low 10 -- ns t 7 address stable to cs or wr high 10 -- ns timing for bit cred r ead operations in uart receive register ; see fig.9 t w(rd) rd pulse width 10 -- ns t rd(urr) rd low to bit cred = 1 t w(rd) +2t cy(clk) - t w(rd) +3t cy(clk) ns t sb(fe) set time bit fe 10.5 -- etu t sb(rbf) set time bit rbf 10.5 -- etu w rite operations in uart transmit register ; see fig.10 t w(wr) wr pulse width 10 -- ns t wr(utr) wr low to i/o low t w(wr) +2t cy(clk) - t w(wr) +3t cy(clk) ns w rite operations in time - out configuration register ; see fig.11 t w(wr) wr pulse width 10 -- ns t wr(toc) wr low to bit cred = 1 note 1 - etu symbol parameter conditions min. typ. max. unit 1 psc ----------- - 2 psc ----------- -
2003 feb 18 42 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 14 application information handbook, full pagewidth rstout c5 i/oaux i/o1 c81 pres1 c41 tda8007bhl ic1 89c51 p0(7:0) cgnd1 clk1 v cc1 rst1 i/o2 c82 1 2 3 4 5 6 7 8 9 10 11 12 c8 rd d7 d6 d5 d4 d3 d2 d1 d0 v dd sam agnd 36 35 34 33 32 31 30 29 28 v ss xtal1 20 19 xtal2 18 p3.7 17 p3.6 16 p3.5 15 p3.4 14 p3.3 13 p3.2 12 p3.1 11 p3.0 10 rst 9 p1.7 8 p1.6 7 p1.5 6 p1.4 5 p1.3 4 p1.2 3 p1.1 2 p1.0 tx rx 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p2.0 p2.1 21 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 psen 29 ale 30 ea 31 p0.7 32 p0.6 33 p0.5 34 p0.4 35 p0.3 36 p0.2 37 p0.1 38 p0.0 39 v cc 40 27 26 25 pres2 c42 cgnd2 clk2 v cc2 rst2 gnd v up sap sbp v dda sbm 13 14 15 16 17 18 19 20 21 22 23 24 delay xtal1 xtal2 ad0 ad1 ad2 ad3 intaux int ale cs wr 48 47 46 45 44 43 42 41 40 39 38 37 22 pf c6 c7 100 nf c3 100 nf c2 100 nf c8 220 nf c12 220 nf c10 100 nf c13 100 nf c14 10 m f (16 v) 100 nf c11 220 nf 100 nf c4 v dd v dd v dd v dd v dd v dd y1 bp1 22 pf c7 c6 c5 c11 c21 c31 c41 k1 k2 c4 card_read_lm01 u2 c3 c2 c1 c51 c61 c71 c81 c8 c1 100 nf c7 c6 c5 c11 c21 c31 c41 k1 k2 c4 card_read_lm01 u1 normally closed switch card 1 card 2 c3 c2 c1 c51 c61 c71 c81 c15 fce690 10 m f (16 v) c9 fig.16 application diagram.
2003 feb 18 43 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 15 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
2003 feb 18 44 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 16 soldering 16.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 16.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 16.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 feb 18 45 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 16.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2003 feb 18 46 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b 17 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 18 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 feb 18 47 philips semiconductors product speci?cation double multiprotocol ic card interface tda8007b notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/06/pp 48 date of release: 2003 feb 18 document order number: 9397 750 10784

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